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8-Bit Microcontroller with Voice ROM
Features
8-bit microcontroller
* * * * * * * *
HT827A0
Operating voltage: 2.4V~5.2V 8K16 program ROM 2088 data RAM 36 bidirectional I/O lines Interrupt input 16-bit programmable timer/event counter with overflow interrupts Watchdog timer On-chip crystal or RC types of oscillator
* * * * * * *
Halt function and wake-up feature reduces power consumption 63 powerful instructions Up to a 1ms instruction cycle with a 4MHz system clock at VDD=5V All instructions in 1 or 2 machine cycles 16-bit table read instruction 8-level subroutine nesting Bit manipulation instruction
Voice and melody synthesizer
* * * * *
128K8 voice ROM 3/4 bit ADPCM coding algorithm 26 kinds of voice sampling rates Tone level of 4 octaves 14 kinds of melody beats
* * * *
Current type of D/A switch output Tone generator counter Controllable volume 48-pin DIP package
Applications
* * *
Intelligent educational toys High end toy controllers Talking alarm clocks
* * *
Alert and warning systems Public address systems Sound effect generators
General Description
The HT827A0 is 8-bit high performance microcontroller with a voice synthesizer and tone generator. They are designed for applications on multiple I/Os with sound effects. The LSIs provide 26 kinds of voice sampling rates, 4 octaves of tone level as well as a high quality of current type D/A output. With such a flexible structure, the HT827A0 is excellent for versatile voice and sound effect product applications. It also includes a halt function to reduce power consumption.
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HT827A0
Block Diagram
IN T TM R V o ic e R O M & C o n tr o lle r V o ic e S y n th e s iz e r & T o n e g e n e ra to r C u rre n t T y p e D /A O u tp u t 3 6 - b it B id ir e c tio n a l I/O P o rts
OSC1 OSC2 RES VDD VSS
8 - b it H ig h P e r fo r m a n c e M ic r o c o n tr o lle r
AUD
PA0 PA7
PB0
PB7
PC0
PC7
PD0
PD7
PE0
PE3
Pin Assignment
PA3 PA2 PA1 NC PA0 PB3 PB2 PB1 PB0 VSS PE0 PE1 PE2 PE3 IN T TM R PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
PB4 PB5 PB6 PB7 PA4 PA5 PA6 PA7 NC NC NC OSC2 OSC1 VDD RES AUD PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
06& %) " & , 12
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HT827A0
Pad Assignment
PA0 PA1 PA2 PA3 PB4 PB6 PB7 PA4 PA6 PA7 PB5 PA5
1
44
43
42
41
40
39
38
37
36
35
34
PB3 PB2 PB1 PB0 VSS
2 3 4 5 6 7 8 9 10 11 12
(0 ,0 )
PE0 PE1 PE2 PE3 IN T TM R
33
OSC2
32 31 30 13
PD0
OSC1 VDD RES AUD
14 15
PD2 PD1
16
PD3
17
PD4
18
PD5
19
PD6
20
PD7
21
PC0
22
PC1
23
PC2
24
PC3
29 25
PC4
26
PC5
27
PC6
28
PC7
Chip size: 3555 5015 (mm)
2
* The IC substrate should be connected to VSS in the PCB layout artwork. * The TMR pad must be bound to VDD or VSS if it is not used.
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HT827A0
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 X -1543.05 -1486.75 -1486.75 -1486.75 -1486.75 -1486.75 -1486.75 -1486.75 -1486.75 -1486.75 -1486.75 -1486.75 -1547.75 -1389.55 -1239.35 -1072.15 -913.45 -744.65 -585.95 -417.15 -258.45 -89.65 Y 2242.95 1675.25 1491.25 1308.95 1126.15 925.35 727.25 538.35 347.85 157.35 -28.35 -219.25 -2211.75 -2211.75 -2211.75 -2211.75 -2211.75 -2211.75 -2211.75 -2211.75 -2211.75 -2211.75 Pad No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 X 69.05 237.85 598.35 890.95 1184.35 1476.95 1507.85 1499.05 1539.95 1585.75 1574.15 1502.55 1227.35 951.35 676.15 396.95 119.35 -159.85 -437.45 -716.65 -991.85 -1267.85 Unit: mm Y -2211.75 -2211.75 -2291.45 -2291.45 -2291.45 -2291.45 -2091.35 -1925.15 -1757.35 -1465.55 -667.75 2242.95 2242.95 2242.95 2242.95 2242.95 2242.95 2242.95 2242.95 2242.95 2242.95 2242.95
Pad Description
Pad No. Pad Name I/O Mask Option Wake-up Pull-high or None Description Bidirectional 8-bit input/output ports Each bit can be configured as a wake-up input by mask option. Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option). Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option). Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option).
1, 44~42, PA0~PA7 37~34
I/O
5~2, 41~38
PB0~PB7
I/O
Pull-high or None
21~28
PC0~PC7
I/O
Pull-high or None
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HT827A0
Pad No. Pad Name I/O Mask Option Pull-high or None 3/4 Pull-high or None Description Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option). Negative power supply, ground Bidirectional 8-bit input/output ports Software instructions determine the CMOS output or schmitt trigger input with or without a pull-high resistor (mask option). External interrupt schmitt trigger input with a pull-high resistor Edge triggered is activated on a high to low transition. Schmitt trigger input for a timer/event counter Audio output for driving an external transistor PMOS open drain output Schmitt trigger reset input, active low Positive power supply
13~20 6 7~10
PD0~PD7 VSS PE0~PE3
I/O 3/4 I/O
11 12 29 30 31 32 33
INT TMR AUD RES VDD OSC1 OSC2
I I O I 3/4 I O
3/4 3/4 3/4 3/4 3/4
OSC1 and OSC2 connect to an RC network or crystal oscillator (determined by mask option) for an internal sysCrystal or tem clock. In the case of RC operation, an oscillation RC resistor connects to OSC1. OSC2 is the output terminal of a 1/4 system clock.
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V Input Voltage .................VSS-0.3V to VDD+0.3V Storage Temperature.................-50C to 125C Operating Temperature ..............-25C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
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HT827A0
D.C. Characteristics
Symbol VDD IDD1 IDD2 ISTB1 ISTB2 VIL VIH VIL1 VIH1 IOL1 IOH1 IOL2 IOH2 RPH IO Parameter Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES, TMR, INT) Input High Voltage (RES, TMR, INT) I/O Port Sink Current (PA, PC, PD, PE) I/O Port Source Current (PA, PC, PD, PE) PB Sink Current PB Source Current Pull-high Resistance of I/O Ports & INT Max. AUD Output Current Test Conditions VDD 3/4 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions 3/4 No load, fSYS=4MHz No load, fSYS=4MHz No load, system Halt No load, system Halt 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V 3/4 3/4 VOH=0.6V VOH=0.6V Min. 2.4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 0 2.4 4.0 0 0 2.4 4.0 2 6 -1 -2 6 20 -0.5 -1 25 10 -1.5 -3.5 Ta=25C Typ. Max. Unit 3/4 1.5 3 1.5 2.5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 4 10 -1.5 -4 10 25 -1 -2 50 30 -2 -4 5.2 3 5 3 5 10 20 3 5 0.6 1.0 3 5 0.6 1.0 3 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 60 3/4 3/4 V mA mA mA mA mA mA mA mA V V V V V V V V mA mA mA mA mA mA mA mA kW kW mA mA
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A.C. Characteristics
Symbol fSYS1 fSYS2 fTIMER tWDTOSC tWDT1 tWDT2 tRES tINT Parameter System Clock (Crystal OSC) System Clock (RC OSC) Timer I/P Frequency (TMR) Watchdog Oscillator Watchdog Timeout Period (RC) Watchdog Timeout Period (System Clock) External Reset Low Pulse Width Interrupt Pulse Width Test Conditions VDD 3V 5V 3V 5V 3V 5V 5V 5V 5V 5V 5V Conditions 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Without WDT prescaler Without WDT prescaler 3/4 3/4 Min. 400 400 400 400 0 0 31 8 3/4 1 1 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 78 20 1024 3/4 3/4 Ta=25C Max. 4000 4000 4000 4000 4000 4000 140 36 3/4 3/4 3/4 Unit kHz kHz kHz kHz kHz kHz ms ms tSYS ms ms
Note: tSYS=1/(fSYS)
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HT827A0
Functional Description
Executive flow The HT827A0 provides a system clock which is derived from a crystal or an RC type of oscillator. The clock is internally divided into four non-overlapping clocks denoted by P1, P2, P3 and P4. An instruction cycle consists of T1~T4. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution take the next instruction cycle. The pipelining scheme causes each instruction to execute effectively in a cycle. If an instruction changes the program counter, two cycles are required to complete that instruction. Program counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed. The contents of the program counter are incremented by one after a program memory word is accessed to fetch an instruction code. The proT1 S y s te m O S C 2 (R C C lo c k o n ly ) P1 P2 P3 P4 PC PC PC+1 PC+2 In te rn a l P hase C lo c k s T2 T3 T4 T1 T2
gram counter then points to a memory word containing the next instruction code. The PC manipulates a program transfer by loading the address corresponding to each instruction when executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine. The conditional skip is activated by instructions. Once the condition is satisfied, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction. Otherwise, the system will proceed with the next instructions. The lower byte of the program counter (PCL) is a readable and writable register (06H). Moving data into PCL performs a short jump. The destination is within 256 locations. Once a control transfer takes place, the execution suffers from an additional dummy cycle.
T3
T4
T1
T2
T3
T4
F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution flow
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HT827A0
Program memory - ROM The program memory stores the to-be-executed program instructions. It also includes data, table and interrupt entries, addressed by the program counter along with the table pointer. The program memory size for HT827A0 is 8K16. Certain locations in the program memory are reserved for special usage:
* Location 000H
000H 004H 008H 00CH D e v ic e in itia liz a tio n p r o g r a m E x te r n a l in te r r u p t s u b r o u tin e S a m p lin g r a te c o u n te r in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e P ro g ra m ROM
L o o k - u p ta b le ( 2 5 6 w o r d s )
This area is reserved for program initialization. The program always begins execution at location 000H each time the system is reset.
* Location 004H
1FFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
Program memory counter overflow, the interrupt is enabled and the stack is not full.
* Location 00CH
This area is reserved for an external interrupt service program. The program begins execution at location 004H if the INT input pin is activated, the interrupt is enabled and the stack is not full.
* Location 008H
This area is reserved for a voice sampling rate counter interrupt service program. The program begins execution at location 008H if a timer interrupt results from a sampling rate Mode Initial reset External interrupt Sampling rate counter overflow Timer/event counter overflow Skip Loading PCL Jump, call branch Return from subroutine *12 *11 *10 #12 #11 #10 *9 #9 *8 #8 S8
This area is reserved for a timer/event counter interrupt service program. The program begins execution at location 00CH if an interrupt results from a timer/event counter overflow, the interrupt is enabled and the stack is not full.
Program Counter *12 *11 *10 0 0 0 0 0 0 0 0 0 0 0 0 *9 0 0 0 0 *8 0 0 0 0 *7 0 0 0 0 @7 #7 S7 *6 0 0 0 0 PC+2 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *5 0 0 0 0 *4 0 0 0 0 *3 0 0 1 1 *2 0 1 0 1 *1 0 0 0 0 *0 0 0 0 0
S12 S11 S10 S9
Program counter Note: *12~*0: Bits of program counter #12~#0: Bits of instruction code S12~S0: Bits of stack register @7~@0: Bits of PCL
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HT827A0
* Table location
Any location in the program ROM can be used a s a l ook - up t a b l e. T he i ns t r u c t i o n s TABRDC [m] (the current page, 1 page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined. The other bits of the table word are transferred to the lower portion of TBLH. The higher-order byte register (TBLH) of the table is read only. The table pointer (TBLP), on the other hand, is a read/write register (07H) indicating the table location. This location must be placed in TBLP before accessing the table. All the table related instructions require 2 cycles to complete an operation. These areas may function as a normal program memory depending upon the users requirements. Stack register - Stack The stack register is a special part of the memory used to save the contents of the program counter (PC). This stack is organized into 8 levels. It is neither part of the data nor program space, and cannot be read or written to. Its activated level is indexed by a stack pointer (SP) and cannot be read or written to. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. The program counter is restored to its previous value from the stack at the end of a subroutine or interrupt routine, which is signaled by a return instruction (RET or RETI). After a chip resets, SP will point to the top of the stack. Instruction(s) TABRDC [m] TABRDL [m]
The interrupt request flag will be recorded but the acknowledgment will be inhibited when the stack is full and a non-masked interrupt takes place. After the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow and allows programmers to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry is lost. Data memory - RAM The data memory is further divided into two functional groups, namely, special function registers and general purpose data memories. Although most of them can be read or be written to, some are read only. The data memory size for HT827A0 is shown as follows. Pard No. HT827A0 Special RAM 00H~2FH General RAM Address 30H~FFH
The special function registers include an indirect addressing register (00H), timer/event counter high byte register (TMRH; 0FH), timer/event counter low byte register (TMRL; 10H); timer/event counter control register (TMRC; 11H), program counter lower-order byte register (PCL; 06H), memory pointer register (MP; 01H), accumulator (ACC; 05H), table pointer (TBLP; 07H), table higher-order byte register (TBLH; 08H), status register (STATUS; 0AH), interrupt control register (INTC; 0BH), watchdog timer option setting register (WDTS; 09H), I/O registers (PA; 12H, PB; 14H, PC; 16H, PD; 18H, PE; 1AH) and I/O Table Location
*12 P12 1
*11 P11 1
*10 P10 1
*9 P9 1
*8 P8 1
*7 @7 @7
*6 @6 @6
*5 @5 @5
*4 @4 @4
*3 @3 @3
*2 @2 @2
*1 @1 @1
*0 @0 @0
Table location Note: *12~*0: Bits of table location @7~@0: Bits of table pointer
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P12~P8: Bits of current program counter
HT827A0
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H G e n e ra l P u rp o s e DATA M EM ORY BEAT TEM PO TONE ROMC DAL DAH VCR SRC TM RH TM RL TM RC PA PAC PB PBC PC PCC PD PDC PE PEC :U nused R e a d a s "0 0 " S p e c ia l P u r p o s e DATA M EM ORY ACC PCL TBLP TBLH W DTS STATUS IN T C In d ir e c t A d d r e s s in g R e g is te r MP
control registers (PAC; 13H, PBC; 15H, PCC; 17H, PDC; 19H, PEC; 1BH). The 20H to 2FH are used for sound and tone (melody) synthesis. The function registers include a lower-order byte register (DAL; 20H) of D/A data, higher-order byte register (DAH;21H) of D/A data , volume control register (VCR; 22H), sampling rate control register (SRC; 23H), beat control register (BEAT; 28H), tempo control register (TEMPO; 29H), tone control register (TONE; 2AH) and voice ROM control register (ROMC; 2CH). The remaining space before 30H is reserved for future expansion. Reading these remaining locations will get 00H. The general purpose data memory is used for data and control information under instruction commands. All of the areas of data memory can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i, and can also be indirectly accessed through a memory pointer register (MP; 01H). Indirect addressing register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation of [00H] accesses the data memory pointed to by MP (01H). Indirectly reading location 00H will return the result to 00H whereas, indirectly writing it will have no effect. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operations. ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
* Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment & decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
ALU not only saves the results of a data operation but also change the status register.
FFH
RAM mapping
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HT827A0
Status register - STATUS This 8-bit register (0AH) consists of a zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except the TO and PD flags, bits in the status register can be altered by instructions similar to other registers. Any data written into the status register will not change the TO or PD flag. Operations related to the status register may yield different results from those intended. The TO and PD flags can be altered only by a watchdog timer overflow, chip power-up, clearing the watchdog time or executing the HALT instruction. The Z, OV, AC and C flags generally reflect the statuses of the latest operations. The status register will not be pushed onto the stack automatically on entering the interrupt sequence or executing the subroutine call. If the status contents are important and the subroutine may corrupt the status register, the programmer must take precautions and save it properly. Labels C Bits 0 Interrupt The HT827A0 provides an external interrupt in addition to two internal timer/event counter interrupts. The interrupt control register (INTC; 0BH) includes interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If an interrupt needs servicing within the service routine, the programmer may set the EMI bit and the corresponding bit of INTC, allowing interrupt nesting. If the stack is full, the interrupt request will not be acknowledged till the SP is decremented, whether or not the related interrupt is enabled. If immediate service is desired, the stack has to be prevented from becoming full. All these interrupts have a wakeup capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. It is also affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or if no borrow from the high nibble into the low nibble in subtraction takes place; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa, otherwise OV is cleared. PD is cleared by a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instructions. TO is set by a WDT time-out. Undefined, read as 0 Undefined, read as 0 STATUS register
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AC Z OV PD TO 3/4 3/4
1 2 3 4 5 6 7
HT827A0
stack and then branching to subroutines at the specified location(s) in the program memory. Only the program counter is pushed onto the stack. The programmer must save the contents of the register or status register (STATUS) in advance if they are altered by an interrupt service program which corrupts the desired control sequence. External interrupts are triggered by a high to low transition of INT. The related interrupt request flag (EIF; bit 4 of INTC) are also set. When an interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The sampling rate counter interrupt is initialized by setting a sampling rate counter interrupt request flag (SRF; bit 5 of INTC), which is caused by a timer overflow. When an interrupt is enabled, the stack is not full and the SRF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (SRF) will be reset and the EMI bit be cleared to disable further interrupts. Register Bit No. 0 1 2 INTC (0BH) 3 4 5 6 7 Label EMI EEI ESI ETI EIF SRF TF 3/4 The internal timer/event counter interrupt is initialized by setting a timer/event counter interrupt request flag (TF; bit 6 of INTC), which is caused by a timer overflow. When an interrupt is enabled, the stack is not full and the TF bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (TF) will be reset and the EMI bit will be cleared to disable further interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgments are all held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from an interrupt subroutine, RET or RETI may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in an interval between the rising edges of two consecutive T2 pulses will be serviced at the latter of the two T2 pulses if the corresponding interrupts are enabled. In the case of simultaneous requests, they can be masked by resetting the EMI bit. The following table illustrates the priority of applying the simultaneous requests: Function Controls a master (global) interrupt (1=enabled; 0=disabled) Controls an external interrupt (1=enabled; 0=disabled) Controls a sampling rate counter interrupt (1=enabled; 0=disabled) Controls a timer/event counter interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) Sampling rate counter request flag (1=active; 0=inactive) Internal timer/event counter request flag (1=active; 0=inactive) Unused bit, read as 0 INTC register
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HT827A0
No. a b c Interrupt Source External Interrupt Sampling Rate Counter Overflow Timer/Event Counter Overflow Priority Vector 1 2 3 04H 08H 0CH
OSC2 C r y s ta l O s c illa to r OSC1 OSC1
fS
YS
/4
OSC2 RC O s c illa to r
System oscillator frequency of the oscillation may vary with VDD, temperature and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is demanded. On the other hand, if a crystal type of oscillator is used instead, a crystal across OSC1 and OSC2 is required, providing feedback and phase shift for the oscillator. No other external components are needed. The resonator can replace the crystal and connects between OSC1 and OSC2 so that a frequency reference can be derived. But two external capacitors in OSC1 and OSC2 are required. The WDT oscillator is a free running on-chip RC oscillator, requiring no external components. The WDT oscillator still works a period of approximately 78ms even when the system enters the power down mode and the system clock is terminated. It nonetheless can be disabled by mask option for conserving power. Watchdog timer - WDT The clock source of WDT is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask option. The watchdog timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. It can be disabled by mask option. After it is disabled, all executions related to WDT are ignored. WDT is first divided by 256 (8 stages) to get a nominal time-out period of 20 ms once an internal WDT oscillator (RC type of oscillator normally with a period of 78ms) is selected. This time-out period may vary with temperature, VDD and process variations. By invoking the
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The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), sampling rate counter interrupt request flag (SRF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable sampling rate counter bit (ESI) and enable master interrupt bit (EMI) make up an interrupt control register (INTC) which is located at 0BH in the data memory. EMI, EEI, ESI and ETI are used to control the enable/disable status of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, SRF, EIF) are all set, they will remain in the INTC register till the interrupts are serviced or cleared by a software instruction. The CALL subroutine is preferably not used within the interrupt subroutine. This is because interrupts often occur in an unpredictable manner or required to be serviced immediately in certain applications. If only one stack is left and enabling the interrupt is not well controlled, operation of the call in the interrupt subroutine will damage the original control sequence. Oscillator configuration The HT827A0 provides two kinds of oscillator circuits, namely, RC and crystal oscillators, for system clocks. Selection of the oscillator circuit type is determined by mask option. When the device enters the HALT mode, the system oscillator stops to conserve power. The system clock is later reset with an external signal. If an RC type of oscillator is used, an external resistor between OSC1 and GND is required and the range of the resistance has to be from 51kW to 1MW. The system, divided by 4, is available on OSC2, which synchronizes external logic. The RC type of oscillator provides the most cost-effective solution. Nonetheless, the
HT827A0
WDT prescaler, a longer time-out period can be attained. Writing data to WS2, WS1 and WS0 (bits 2, 1 and 0 of WDTS) can derive different time-out periods. If WS2, WS1 and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 WDTS register If the WDT oscillator is disabled, the WDT clock may still come from an instruction clock. It operates in the same manner except that WDT may stop counting and loses its protecting purpose in the HALT state. In this situation the logic can only be re-initialized by external logic. The high nibble and bit 3 of WDTS are reserved for users defined flags. The programmer may use these flags to indicate some specified statuses. The on-chip RC oscillator (WDT OSC) is strongly recommended if the device operates in a noisy environment, since the HALT function will stop the system clock. Overflow of the WDT under a normal operation initializes a chip reset and sets the status bit TO. It will initialize a warm reset, and only PC and SP are reset to zero in the HALT mode.
S y s te m C lo c k /4 M ask O p tio n S e le c tio n W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
To clear the contents of WDT (including the WDT prescaler), three methods are adopted, namely, external reset (a low level to RES), software instructions, and HALT instruction. The software instructions include CLR WDT and the other sets - CLR WDT1 and CLR WDT2. Of these two types of instructions, by mask option only one can be active at a time CLR WDT times selection option. If CLR WDT is chosen (i.e., CLRWDT times equal one), any execution of the CLR WDT instruction will clear WDT. In the case that CLR WDT1 and CLR WDT2 are selected (i.e., CLRWDT times equal two), these two instructions must be executed to clear WDT; otherwise WDT may reset the chip as a result of time-out. Power down operation - HALT The HALT mode is initialized by the HALT instruction and results in the following:
* The system oscillator is turned off but the
* *
* *
WDT oscillator still keeps running (if the WDT oscillator is selected). The contents of the on-chip RAM and registers remain unchanged. The WDT and WDT prescaler are cleared and re-counted (if the clock of WDT is from the WDT oscillator). All the I/O ports maintain their original statuses. The PD flag is set and the TO flag cleared.
The system can quit the HALT mode by an external reset, interrupt, external falling edge signal on port A or WDT overflow. An external reset leads to device initialization and a WDT overflow performs a warm reset. The reason for chip re-
W DT OSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog timer
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March 15, 2000
HT827A0
set can then be determined after examining the TO and PD flags. The PD flag is cleared when the system powers up or executes the CLR WDT instruction and set when the HALT instruction is executed. The TO flag is set if the WDT time-out occurs, and causes a wake-up that resets only the PC and SP. The others maintain their original statuses. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. However, if it is awakening from an interrupt, two sequences may happen. The program will resume execution at the next instruction if the related interrupt is disabled or the it is enabled but the stack is full. Nonetheless, if the interrupt is enabled and the stack is not full, a regular interrupt response takes place. Once the wake-up event occurs, and the system clock comes from a crystal, it takes 1024 tSYS (system clock period) to resume a normal operation. In other words, the HT827A0 will insert a dummy period after the wake-up. If the system clock, on the other hand, is from an RC type of oscillator, it will continue operation. The actual interrupt subroutine execution will be delayed by one or more cycles if the wake-up results from an interrupt acknowledgment. On the other hand, it will be executed immediately after the dummy period is finished if the wake-up results in the next instruction execution. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT mode. Reset There are three ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during a normal operation
their original states. Some registers will remain unchanged during reset conditions. Most registers are reset to the initial condition once the reset conditions are met. The program can distinguish between different chip resets by examining the PD flag and TO flag. TO PD 0 u 0 1 1 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
Note: u means unchanged To guarantee that the crystal oscillator is started and stabilized, XST (Crystal Start-up Timer) provides an extra-delay by an OSC mask option. The extra-delay delays 1024 system clock pulses when the system awakes from the HALT state or from system power-up and the RES transforms low to high. XST is automatically selected if the crystal oscillator is invoked. On the other hand, it is disabled when the RC oscillator is chosen. The XST delay is added after XST is chosen and awakening from the HALT state or the system powers up. The reset duration comes only from RES if an RC oscillator is selected. An extra delay, on the other hand, is added during the power-up period and any wakeup from HALT only if a crystal oscillator is chosen instead. The HT827A0 provides another useful feature for purposes of testing and synchronization. Releasing RES high will start execution if RES keeps low long enough.
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm reset that resets only the PC and SP, leaving the other circuits to remain in
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HT827A0
The chip reset status are shown below: PC Interrupt Prescaler WDT Timer/Event Counter Input/Output Ports SP
V
DD
Code 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx
Volume 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16
Code 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 xxxx
Volume 9/16 10/16 11/16 12/16 13/16 14/16 15/16 16/16
0000H Disabled Cleared Cleared. After a master reset, WDT begins counting. Off Input mode Point to the top of the stack.
Volume level table Note: xx means dont care
RES
Reset circuit Audio output and volume control The HT827A0 provides a current type D/A output for driving external 8W speaker through an external NPN transistor. The user must write the voice data to the register DAL (20H) and DAH (21H). Only 12 bits which include the high nibble of DAL and the whole byte of DAH are used. For the current type D/A output the high nibble data of DAL must be written at first, and then the DAH data is written. There are 16 steps of volume controllable level that are provided for the current type D/A output. The user only writes the volume control data to the VCR register (22H). Only the high nibble of VCR are used. Note that writing 0H to the high nibble of VCR doesnt denote mute output. When bit 7 (SRON) of the TEMPO register (29H) is set as 1 the change of volume level is valid. The following is a table of the 16 kinds of volume level:
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HT827A0
The states of the registers are summarized in the following table: Register TMRH TMRL TMRC PC MP ACC TBLP TBLH STATUS INTC WDTS PA PAC PB PBC PC PCC PD PDC PE PEC DAL DAH VCR SRC BEAT TEMPO TONE Reset (Power On) xxxx xxxx xxxx xxxx 00-0 1--0000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 ---0000 0000 0000 -----xx xxxx xxxx xxxx 00-- xxxx 0-xx xxxx WDT Time-out (Normal Operation) uuuu uuuu uuuu uuuu 00-0 1--0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 ---0000 0000 0000 -----uu uuuu uuuu uuuu 00-- uuuu 0-uu uuuu RES Reset (Normal Operation) uuuu uuuu uuuu uuuu 00-0 1--0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 ---0000 0000 0000 -----uu uuuu uuuu uuuu 00-- uuuu 0-uu uuuu RES Reset (HALT) uuuu uuuu uuuu uuuu 00-0 1--0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu -000 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 ---0000 0000 0000 -----uu uuuu uuuu uuuu 00-- uuuu 0-uu uuuu WDT Time-out (HALT)* uuuu uuuu uuuu uuuu uu-u u--0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu 0000 ---0000 0000 0000 -----uu uuuu uuuu uuuu 00-- uuuu 0-uu uuuu
Note: * means warm reset u means unchanged x means unknown
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HT827A0
Sampling rate counter The HT827A0 offers a sampling rate counter. This counter contains a 5 bit programmable count-up counter. The clock may come from 128kHz or 2kHz by code option and the clock base on 3.579545MHz system clock. Labels SR0~ SR4 2K/ 128K 3/4 Bit s Function Code Freq. Code Freq. xx00 1010 5.08kHz xx00 1011 5.33kHz xx00 1100 5.59kHz xx01 0111 12.43kHz xx01 1000 13.98kHz xx01 1001 15.98kHz
Sampling rate table Note: xx means dont care On the other hand, when the 2kHz clock is chosen, 32 kinds of time periods of the envelope decay is offered. The following is a table of the envelope decay: Code Freq. Code xx11 0000 xx11 0001 xx11 0010 xx11 0011 xx11 0100 xx11 0101 xx11 0110 xx11 0111 xx11 1000 xx11 1001 xx11 1010 xx11 1011 xx11 1100 xx11 1101 xx11 1110 Freq. 109.3Hz 116.5Hz 124.9Hz 134.5Hz 145.7Hz 158.9Hz 174.8Hz 194.2Hz 218.5Hz 249.7Hz 291.3Hz 349.6Hz 437.0Hz 582.7Hz 874.0Hz 1.75kHz xx10 0000 54.6Hz xx10 0001 56.4Hz
DATA BUS
To define a voice sampling 0~4 rate or envelope decaying time 5 To define an input clock source (0=128K; 1=2K)
6~7 Unused bits, read as 0 SRC register
128K
xx10 0010 58.3Hz xx10 0011 60.3Hz xx10 0100 62.4Hz xx10 0101 64.7Hz
2K
S a m p lin g R a te C o u n te r P r e lo a d R e g is te r
R ELO AD
2 K /1 2 8 K
SRON
S a m p lin g R a te C o u n te r
1 C o u n te r
O VERFLO W to In te rru p t
xx10 0110 67.2Hz xx10 0111 69.9Hz xx10 1000 72.8Hz xx10 1001 76.0Hz xx10 1010 79.5Hz xx10 1011 83.2Hz xx10 1100 87.4Hz xx10 1101 92.0Hz xx10 1110 97.1Hz
Sample rate counter When the 128kHz clock is selected, 26 kinds of sampling rate are provided for a voice synthesizer. The following is a table of the 26 kinds of sampling rates: Code Freq. Code Freq. xx00 0000 3.50kHz xx00 0001 3.61kHz xx00 0010 3.72kHz xx00 0011 3.86kHz xx00 0100 3.99kHz xx00 0101 4.14kHz xx00 0110 4.30kHz xx00 0111 4.48kHz xx00 1000 4.66kHz xx00 1001 4.86kHz xx00 1101 5.89kHz xx00 1110 6.21kHz xx00 1111 6.58kHz xx01 0000 6.99kHz xx01 0001 7.46kHz xx01 0010 7.99kHz xx01 0011 8.61kHz xx01 0100 9.32kHz xx01 0101 10.17kHz xx01 0110 11.19kHz
19
xx10 1111 102.8Hz xx11 1111 Envelope decay table Note: xx means dont care
March 15, 2000
HT827A0
One of the relative counter values is preloaded to the sampling rate counter after a code is written to the counter (SRC; 23H). Once the sampling rate counter starts counting, it will count from its current contents to 1FH. The counter is reloaded from the sampling rate counter preload register, and generates an interrupt request flag (SRF; bit 5 of INTC) if overflow of the divide-by-1 counter occurs. To enable a counting operation, the ON bit (SRON; bit 7 of TEMPO) of the counter should be set to 1. Overflow of the sampling rate counter is one of the wake-up sources. Writing a 0 to ESI will disable the interrupt service. Writing data to the sampling rate preload register will also reload the data to the sampling rate counter in the case of 1F condition of the sampling rate counter. On the other hand, data written to the sampling rate counter will be kept only in the counter preload register if the counter is turned on. The sampling rate counter still goes on working till an overflow of the divide-by-1 counter occurs.
S y s te m TM R0 TM R1 TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /e v e n t C o u n te r C lo c k /4
The clock is blocked to avoid errors once the sampling rate counter is read. The programmer should take the counting error into account since blocking of the clock may result in a counting error. Timer/event counter The HT827A0 provides a timer/event counter. This timer contains an 8-bit/16-bit programmable count-up counter. The clock may come from an external source or from the system clock divided by 4. Only one reference time-base is available when an internal instruction clock is selected. The external clock input allows the user to count external events, measure time intervals or pulse widths, or generate an accurate time base. For the 16-bit timer/event counter, there are three registers related to the timer/event counter, namely, TMRH ([0FH]), TMRL ([10H]) and TMRC ([11H]). Three physical registers are mapped to the TMR location. Writing TMRL only writes the data into a low byte buffer, and writing
DATA BUS
TM 1 TM 0
T im e r /e v e n t C o u n te r P r e lo a d R e g is te r
R ELO AD
O VERFLO W T o In te rru p t
L o w B y te B u ffe r
16-bit Timer/event counter
S y s te m TM R TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /e v e n t C o u n te r C lo c k /4 DATA BUS TM 1 TM 0 T im e r /e v e n t C o u n te r P r e lo a d R e g is te r RELO AD
O VERFLO W T o In te rru p t
8-bit Timer/event counter
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HT827A0
TMRH will write the data and the content of the low byte buffer into the timer/event counter preload register (16-bit) simultaneously. The timer/event counter preload register is changed by writing TMRH operations and writing TMRL will keep the timer/event counter preload register unchanged. Reading TMRH will also latch the TMRL into the low byte buffer to avoid the false timing problem. Reading TMRL returns the content of the low byte buffer. In other words, the low byte of the timer/event counter can not be read directly. It must read the TMRH first to make the low byte content of the timer/event counter latched into the buffer. For the 8-bit timer/event counter, TMRH is undefined. Writing TMRL makes the starting value be placed in the timer/event counter preload register and reading it gets the contents of the timer/event counter. TMRC is a timer/event counter control register which defines some options. The TM0 and TM1 bits define the operation mode. The event counting mode counts external events, indicating that the source of the clock is from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from an instruction clock. The pulse width measurement mode can be used to count a high to low level duration of an external signal (TMR). This counting is based on the instruction clock. In the event counting or timer mode, after the timer/event counter starts counting, it will count from its current contents to FFFFH for 16-bit timer/event counter or FFH for 8-bit timer/event counter. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register and generates an interrupt request flag (TF; bit 6 of INTC). In the pulse width measurement mode with the TON and TE bits equal to one, after TMR transition from low to high (or high to low when the TE bit is 0), it will start counting till it returns to the original level and resets the TON. The m e a s ur ed r es ul t s t i l l r em a i ns i n t h e timer/event counter even when the activated transition re-occurs. In other words, only one
21 March 15, 2000
cycle can be measured till TON is set. The cycle measurement will go on functioning as long as further transient pulses are received. In this operation mode, the timer/event counter starts counting not according to the logic level but to the transient edges. In the case of a counter overflow, the counter is reloaded from the timer/event counter preload register and issues an interrupt request, like the other two modes. The timer ON bit (TON; bit 4 of TMRC) should be set to 1 to enable a counting operation. In the pulse width measurement mode, TON will be cleared automatically after the measurement cycle is completed. In the other two modes, TON can be reset only by instructions. The overflow of the timer/event counter is one of the wake-up sources. Writing a 0 to ETI will disable the interrupt service no matter what kind of operation mode is chosen. In the case of the timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload it to the timer/event counter. Data written to the timer/event counter will however be kept in the timer/event counter preload register if the timer/event counter is turned on. It will keep on operating till an overflow occurs. The clock will be blocked to avoid errors when the timer/event counter (reading TMR) is read. The programmer should take the counting error into account since clock blocking may result in a counting error.
HT827A0
Labels (TMRC) 3/4 TE TON 3/4 TM0 TM1 Bits 0~2 3 4 5 6 7 Unused bits, read as 0 To define the TMR active edge of a timer/event counter (0=active on low to high; 1=active on high to low) To enable/disable timer counting (0=disabled; 1=enabled) Unused bits, read as 0 To define the operation mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC register Tone and melody generator The HT827A0 provides a tone frequency register (TONE; 2AH), beat frequency register (BEAT; 28H) as well as tempo frequency register (TEMPO; 29H) for generating melody and sound effects. The chip can generate four octaves, labeled from C2# to C6. Desired frequencies can be obtained by first writing the related data into a tone frequency register (TONE; 2AH) and then enabling the tone counter. A Tone frequency is generated and remained if the tone counter overflows. Labels TN0~ TN3 OCT0 OCT1 3/4 TEN Bits 0~3 4 5 6 7 Function To define the tone frequency (refer to the tone frequency table) To define the 4 octave tone frequencies (refer to the tone frequency table) Unused bit, read as 0 To enable/disable the tone counter (0= disabled; 1= enabled) TONE register
T o n e R e g is te r DATA BUS
Function
T o n e F re q u e n c y P L A T a b le
128kH z TEN
T o n e C o u n te r
T o n e F re q u e n c y
TONE counter The BEAT register counts melody beats. Bit 7 (BTO) of the BEAT register is set when the beat counter overflows. No interrupt is generated if the beat counter overflows. So bit 7 (BTO) of the BEAT register must be polled to generate correct beat frequencies. After reading the BTO status, the bit 7 should be cleared by the programmer to avoid malfunction of the next polling. Labels Bits B0~B6 BTO 0~6 7 Function To define the beat frequency (refer to the beat frequency table) BTO is set during beat counter time-out BEAT register
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Code 1x00 0000 1x00 0001 1x00 0010 1x00 0011 1x00 0100 1x00 0101 1x00 0110 1x00 0111 1x00 1000 1x00 1001 1x00 1010 1x00 1011 1x00 1100 1x00 1101 1x00 1110 1x00 1111 1x01 0000 1x01 0001 1x01 0010 1x01 0011 1x01 0100 1x01 0101 1x01 0110 1x01 0111 1x01 1000 1x01 1001 1x01 1010 1x01 1011 1x01 1100 1x01 1101 1x01 1110 1x01 1111 Frequency 3/4 138.5Hz 146.4Hz 155.4Hz 164.5Hz 174.8Hz 185.2Hz 195.6Hz 207.2Hz 220.2Hz 233.1Hz 247.5Hz 261.4Hz 3/4 3/4 3/4 3/4 279.6Hz 292.9Hz 310.8Hz 329.0Hz 349.6Hz 370.4Hz 391.2Hz 414.4Hz 440.5Hz 466.1Hz 495.0Hz 522.8Hz 3/4 3/4 3/4 Tone 3/4 C2
#
Code 1x10 0000 1x10 0001 1x10 0010 1x10 0011 1x10 0100 1x10 0101 1x10 0110 1x10 0111 1x10 1000 1x10 1001 1x10 1010 1x10 1011 1x10 1100 1x10 1101 1x10 1110 1x10 1111 1x11 0000 1x11 0001 1x11 0010 1x11 0011 1x11 0100 1x11 0101 1x11 0110 1x11 0111 1x11 1000 1x11 1001 1x11 1010 1x11 1011 1x11 1100 1x11 1101 1x11 1110 1x11 1111
Frequency 3/4 553.8Hz 585.7Hz 621.5Hz 658.1Hz 699.2Hz 740.9Hz 782.3Hz 828.7Hz 880.9Hz 932.3Hz 990.0Hz 1045.6Hz 3/4 3/4 3/4 3/4 1107.7Hz 1171.5Hz 1243.1Hz 1316.2Hz 1398.4Hz 1481.8Hz 1564.7Hz 1657.4Hz 1761.8Hz 1864.6Hz 1980.1Hz 2091.1Hz 3/4 3/4 3/4
Tone 3/4 C4
#
D2 D2 E2 F2 F2
#
D4 D4 E4 F4 F4
#
#
#
G2 G2 A2 A2 C3 3/4 3/4 3/4 3/4 C3 B2
#
G4 G4 A4 A4 B4 C5 3/4 3/4 3/4 3/4 C5
#
#
#
#
#
D3 D3 E3 F3 F3
#
D5 D5 E5 F5 F5
#
#
#
G3 G3 A3 A3 C4 3/4 3/4 3/4 B3
#
G5 G5 A5 A5 B5 C6 3/4 3/4 3/4
#
#
#
TONE frequency table Note: x means dont care 3/4 means invalid
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HT827A0
Code 1xxx xxxx 0000 0000 0000 0010 0000 0011 0000 0101 0000 0111 0000 1011 0000 1111 0001 0001 0001 0111 0010 0011 0010 1111 0100 0100 0101 1111 0111 0111 Other codes Beat Beat time-out 1/24 Beat 1/8 Beat 1/6 Beat 1/4 Beat 1/3 Beat 1/2 Beat 2/3 Beat 3/4 Beat 1 Beat 3/2 Beat 2 Beats 3 Beats 4 Beats 5 Beats 3/4 Code 0000 0001 0010 0011 0100 0101 0110
DATA BUS B e a t fre q u e n c y ta b le P L A
Labels Bits TN0~ TN3 3/4 TMPEN
Function
To define the tempo frequency 0~3 (refer to the tempo frequency table) 4,5 6 Unused bits, read as 0 To enable/disable the tempo counter (0=disabled; 1=enabled) To enable/disable the D/A output, sampling rate counter and voice ROM (0=disabled; 1=enabled) TEMPO register TEMPO CLK 30.5Hz 32.55Hz 34.88Hz 37.56Hz 40.69Hz 44.39Hz 48.83Hz 54.25Hz 61Hz 65.1Hz 69.8Hz 75.12Hz 81.38Hz 88.78Hz 97.66Hz 108.5Hz TEMPO BPM 68.3 72.8 78.0 84.0 91.0 99.3 109.3 121.4 136.6 145.7 156.1 168.1 182.1 198.6 218.5 242.8
SRON
7
BEAT frequency table Note: 3/4 means unknown beats
0111 1000 1001 1010
2kH z TEN
B e a t c o u n te r
S e t th e B T O
1011 1100
BEAT counter The TEMPO register counts melodies. A tempo frequency is generated after tempo data are loaded and the TEMPO counter is also enabled. The tempo determines the beat time period. When the SRON bit of TEMPO register be clear as 0, the TMPEN0 is automatic occur at the same time. That is to say, if SRON=0, TMPEN always equals 0.
1101 1110 1111
TEMPO frequency table
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HT827A0
Voice ROM The HT827A0 includes a ROM for storing sound and tone (melody) data. Coded data can be saved in an internal mask ROM by changing one layer of the mask after the sound and tone (melody) sources are coded by Holteks tools. The voice ROM size for HT827A0 is 128K8. The handshaking between the microcontroller and voice ROM is through a ROM control register (ROMC; 2CH). To enable the voice ROM, the bit 7 of the TEMPO register should be set as 1. The related ROM address has to be saved in the ROM control register first if the microcontroller attempts to read the sound or tone (melody) data in the mask ROM. The ROM is comprised by a set of address counters internally. After the microcontroller finishes reading a byte of data, its internal address counter will automatically be increased by one. In this case, reading continuous data only requires loading the starting address to the ROM control register. The lower-order nibble is valid whereas the higher-order nibble is not valid in the ROM control register. Based on this difference, the start address has to be divided into six nibbles, and written into the ROM control register six times with respect to the divided-by-six nibbles. The lower-order nibble and higher-order nibble data can then be read back by reading twice after the sound or tone (melody) starting address is written. Every times of reading must interval at least fifty instruction cycles after the address is exchanged or fore reading. For example, if the
AD0~AD3 ROMC A d d re s s C o u n te r A d d re s s C o u n te r A d d re s s C o u n te r WR A d d re s s C o u n te r RD 2
A1X~A12
starting address of the sound data to be read is 0CF0H, the program of reading one byte of sound or tone (melody) data is as follows: Read-New-Data: SET MOV A, 00H MOV [ROMC], A; MOV A,0FH MOV[ROMC], A; MOV A, 0CH MOV [ROMC], A; MOV A, 00H MOV [ROMC], A; MOV A, 00H MOV [ROMC] MOV A, 00H MOV [ROMC], A CALL DELAY; MOV A, [ROMC]; MOV [DATA], A; MOV A, [ROMC]; Read the high-order nibble data Write the fourth nibble address Write the fith nibble address Writh the sixth nibble address Delay 50 instruction cycles Read the lower-order nibble data Write the third nibble address Write the second nibble address Write the first nibble address TEMPO.7
A11~A8
D4~D7
A7~A4
V o ic e ROM
D a ta R e g is te r ( h ig h n ib b le )
D0~D3
D a ta R e g is te r ( lo w n ib b le )
RD
A3~A0
EN T E M P O .7 X=4,5 or6
Voice ROM
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SWAPA [ACC]; ORM A, [DATA]; Combine the lower-order data and higher-order data it is 0, the contents of the latches will move to the internal bus. The latter is possible only in the read-modify-write instruction. For the output function, CMOS is the only configuration. These control registers are all mapped to locations 13H, 15H, 17H, 19H, 1BH. The PE hi-nibble bits are void, this four bits are read as 0. These input/output lines stay at a high level or floating (decided by mask option) after a chip reset. Each bit of the input/output latches can be set or cleared by the SET[m].i and CLR[m].i (m=12H, 14H, 16H, 18H, 1AH) instructions. Some instructions will first input data and then follow the output operations. For instance, SET[m].i, CLR[m].i, CPL[m], and CPLA[m] read the entire port state into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or accumulator. Each line of port A is capable of waking up the device. The highest four bits of port E are not physically implemented. A 0 will return to reading the highest four bits, but writing them will result with no operation.
Input/Output ports The HT827A0 includes 36 bidirectional input/output lines, labeled from PA to PC or PE which are mapped to the data memories of [12H], [14H], [16H], [18H] and [1AH], respectively. All of these I/O ports can be used as input and output operations. For input operation, these ports are non-latched, i.e., the inputs must be ready at the T2 rising edge of the instruction MOV A, [m] (m=12, 14, 16H, 18H or 1AH). For output operation, all the data are latched and remain unchanged till the output latch is re-written. Each I/O line has its own control register (PAC, PBC, PCC, PDC and PEC) to control the input/output configuration. With a control register, a CMOS output or schmitt trigger input can be re-configured dynamically (i.e., on-the-fly) with or without pull-high resistor structures under a software control. To function as an input, the corresponding latch of a control register must write 1. The pull-high resistance will be automatically exhibited if the pull-high option is chosen. The input source also depends on the control register. If the bit of the control register bit 1, the input will read the pad state. If
DATA BUS W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D W r ite I/O CK S Q M R e a d I/O S y s te m W a k e - u p ( P A o n ly ) M a s k O p tio n U X Q D CK S Q Q
V V
DD
DD
W EAK P u ll- u p M a s k O p tio n PA0 PB0 PC0 PD0 PE0 ~PA ~PB ~PC ~PD ~PE 3 7 7 7 7
Input/Output ports
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Mask option The following table illustrates 5 kinds of mask option in the HT827A0. All of them have to be defined to ensure a proper functioning system. No. 1 Mask Option OSC type selection This option determines the selection of a system clock, whether an RC or crystal type of oscillator. WDT source selection Three selections are provided, namely, on-chip RC oscillator, instruction clock and WDT disable. CLRWDT times selection This option defines clearing WDT by instructions. Once means CLR WDT can clear WDT. Twice means WDT can be cleared only if both CLR WDT1 and CLR WDT2 are executed. Wake-up selection This option defines the activity of the wake-up function. All of the external I/O pins (PA only) are capable of waking up the chip from a HALT mode. Pull-high selection This option determines whether or not the pull-high resistance exists in the input mode of the I/O ports. Each bit of the I/O port can be independently selected.
2
3
4
5
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Application Circuits
RC oscillator for multiple I/O applications Crystal oscillator for multiple I/O applications
20pF OSC1 OSC2 V 10kW RES 0 .1 m F
DD
R
OSC
PA0~PA7 PB0~PB7 PC 0~PC 7 PD 0~PD 7 PE0~PE3 V
DD
OSC1 10M W 20pF V OSC2
DD
PA0~PA7 PB0~PB7 PC 0~PC 7 PD 0~PD 7
fS
YS
/4
10kW RES SPK 8W 0 .1 m F
PE0~PE3
V
DD
SPK 8W IN T TM R AUD 8050
IN T TM R
AUD
8050
06&
%)
06&
%)
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Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry None None C C None None C C AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to register with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry leaving result in the data memory Decimal adjust ACC for addition with result in data memory Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Flag Affected
Increment & Decrement
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Mnemonic Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear data memory Set data memory Clear Watchdog timer Pre-clear Watchdog timer Pre-clear Watchdog timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode None None None TO,PD TO*,PD* TO*,PD* None None TO,PD Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt None None None None None None None None None None None None None Clear bit of data memory Set bit of data memory None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC None None None Description Flag Affected
Note: x: 8-bit immediate data m: 7-bit data memory address A: Accumulator i: 0~7 number of bits addr: 11-bit program memory address O: Flag(s) is affected -: Flag(s) is unaffected *: Flag(s) may be affected by the execution status
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Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add data memory and carry to accumulator The contents of the specified data memory accumulator and carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add accumulator and carry to data memory The contents of the specified data memory accumulator and carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to accumulator The contents of the specified data memory and accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to accumulator The contents of the accumulator and specified data are added, leaving the result in the accumulator. ACC ACC+x
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ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add accumulator to data memory The contents of the specified data memory and accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Logical AND accumulator with data memory Data in the accumulator and specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to accumulator Data in the accumulator and specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with accumulator Data in the specified data memory and accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
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CALL addr Description Subroutine call The instruction unconditionally calls a subroutine which is located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr TC2 3/4 CLR [m] Description Operation Affected flag(s) TC2 3/4 CLR [m].i Description Operation Affected flag(s) TC2 3/4 CLR WDT Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Clear data memory The contents of the specified data memory are cleared to zero. [m] 00H
Clear bit of data memory Bit i of the specified data memory is cleared to zero. [m].i 0
Clear watchdog timer The WDT and WDT Prescaler are cleared (re-count from zero). The power down bit (PD) and time-out bit (TO) are both cleared. WDT & WDT Prescaler 00H PD & TO 0
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CLR WDT1 Description Preclear watchdog timer The PD, TO flags, WDT and the WDT Prescaler are all cleared (re-count from zero) if the other preclear WDT instruction has been executed. Execution only of this instruction without the other preclear instruction sets the indicated flag, which implies that this instruction is executed and the PD and TO flags remain unchanged. WDT & WDT Prescaler 00H* PD & TO 0* TC2 3/4 CLR WDT2 Description TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Preclear watchdog timer The PD, TO flags, WDT and the WDT Prescaler are all cleared (re-count from zero) if the other preclear WDT instruction has been executed. Execution only of this instruction without the other preclear instruction sets the indicated flag, which implies that this instruction is executed and the PD and TO flags remain unchanged. WDT & WDT Prescaler 00H* PD & TO 0* TC2 3/4 TC1 3/4 TO 0* PD 0* OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
CPL [m] Description
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a one are changed to zero and vice-versa. [m] [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
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CPLA [m] Description Complement data memory place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a one are changed to zero and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m] TC2 3/4 DAA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Decimal-Adjust accumulator for addition The value of the accumulator is adjusted to a BCD (Binary Code Decimal) code. If bits 0~3 of the accumulator are greater than 9 or AC is one, six is added to the low-order nibble of the accumulator, deriving a BCD digit in the low-order nibble. Similarly, if bits 4~7 of the accumulator are greater than nine or C is one, six is added to the high-order nibble of the accumulator, generating a BCD digit in the high-order nibble. The result is stored in the data memory. If ACC.3~ACC.0 >9 or AC=1 then ([m].3~[m].0) (ACC.3~ACC.0)+6 else ([m].3~[m].0) (ACC.3~ACC.0) and If ACC.7~ACC.4 >9 or C=1 then ([m].7~[m].4) (ACC.7~ACC.4)+6,C=1 else ([m].7~[m].4) (ACC.7~ACC.4),C=C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
DEC [m] Description Operation Affected flag(s)
Decrement data memory Data in the specified data memory are decremented by one. [m] [m]-1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
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DECA [m] Description Decrement data memory place result in the accumulator Data in the specified data memory are decremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1 TC2 3/4 HALT Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0 TC2 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation
Affected flag(s)
INC [m] Description Operation Affected flag(s)
Increment data memory Data in the specified data memory are incremented by one. [m] [m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
INCA [m] Description
Increment data memory-place result in accumulator Data in the specified data memory are incremented by one, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
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JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Direct Jump Bits 0~10 of the program counter are unconditionally replaced with the directly-specified addresses, and the control is passed to this destination. PC addr
Move data memory to accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Move immediate data to accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move accumulator to the data memory The contents of the accumulator are copied to the specified data memory (one of the data memory). [m] ACC
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NOP Description Operation Affected flag(s) TC2 3/4 OR A,[m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 No operation No operation is performed. Execution continues with the next instruction. PC PC+1
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memory) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
OR A,x Description Operation Affected flag(s)
Logical OR immediate data to accumulator Data in the accumulator and specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
ORM A,[m] Description Operation Affected flag(s)
Logical OR data memory with accumulator Data in the data memory (one of the data memory) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
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RET Description Operation Affected flag(s) TC2 3/4 RET A,x Description Operation Affected flag(s) TC2 3/4 RETI Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a two-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator is loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts enabled by setting the EMI bit. EMI is an enable master (global) interrupt bit (bit 0; register INTC). PC Stack EMI 1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
RL [m] Description Operation Affected flag(s)
Rotate data memory left The contents of the specified data memory are rotated 1 bit to the left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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RLA [m] Description Rotate data memory to the left - then place result in the accumulator Data in the specified data memory are rotated 1-bit to the left with bit 7 rotated into bit 0, leaving the rotation result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 TC2 3/4 RLC [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Rotate data memory left through carry The contents of the specified data memory and carry flag are rotated 1-bit to the left. Bit 7 replaces the carry bit; the original carry flag is rotated to the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
RLCA [m] Description
Rotate left through carry - then place result in the accumulator Data in the specified data memory and carry flag are rotated 1-bit left. Bit 7 replaces the carry bit and the original carry flag is rotated to the bit 0 position. The rotation result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
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RR [m] Description Operation Affected flag(s) TC2 3/4 RRA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Rotate data memory to the right The contents of the specified data memory are rotated 1-bit to the right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate to the right - then place result in the accumulator Data in the specified data memory are rotated 1-bit to the right with bit 0 rotated to bit 7, leaving the rotation result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
RRC [m] Description
Rotate data memory to the right through carry The contents of the specified data memory and carry flag are rotated 1-bit to the right. Bit 0 replaces the carry bit; the original carry flag is rotated to the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
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RRCA [m] Description Rotate to the right through carry - then place result in the accumulator Data of the specified data memory and carry flag are rotated one bit right. Bit 0 replaces the carry bit and the original carry flag is rotated to the bit 7 position. The rotation result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0 TC2 3/4 SBC A,[m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Operation
Affected flag(s)
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
Operation Affected flag(s)
SBCM A,[m] Description
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O
Operation Affected flag(s)
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SDZ [m] Description Skip if decrement data memory is zero The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped and the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get a proper instruction. This makes a 2-cycle instruction. Otherwise proceed to the next instruction. Skip if ([m]-1)=0, [m] ([m]-1) TC2 3/4 SDZA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Decrement data memory - then place result in ACC, skip if zero The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get a proper instruction, making a 2-cycle instruction. Otherwise proceed to the next instruction. Skip if ([m]-1)=0, ACC ([m]-1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SET [m] Description Operation Affected flag(s)
Set data memory Each bit of the specified data memory is set to 1 [m] FFH TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
SET [m].i Description Operation Affected flag(s)
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
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SIZ [m] Description Skip if increment data memory is zero The contents of the specified data memory are incremented by one. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction. Skip if ([m]+1)=0, [m] ([m]+1) TC2 3/4 SIZA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Increment data memory - then place result in ACC, skip if zero The contents of the specified data memory are incremented by one. If the result is zero, the next instruction is skipped and the result stored in the accumulator. The data memory remains unchanged. If the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get a proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction. Skip if ([m]+1)=0, ACC ([m]+1) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SNZ [m].i Description
Skip if bit i of the data memory is not zero If bit i of the specified data memory is not zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get a proper instruction. This is a 2 cycle instruction. Otherwise proceed with the next instruction. Skip if [m].i0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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SUB A,[m] Description Operation Affected flag(s) TC2 3/4 SUBM A,[m] Description Operation Affected flag(s) TC2 3/4 SUB A,x Description Operation Affected flag(s) TC2 3/4 SWAP [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (one of the data memory) are interchanged. [m].3~[m].0 [m].7~[m].4
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HT827A0
SWAPA [m] description Swap data memory - then place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 TC2 3/4 SZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Skip if data memory is zero If the contents of the specified data memory are zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get a proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction. Skip if [m]=0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
SZA [m] Description
Move data memory to ACC, skip if zero The contents of the specified data memory are copied to the accumulator. If the contents are zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get a proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction. Skip if [m]=0 TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
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March 15, 2000
HT827A0
SZ [m].i Description Skip if bit i of the data memory is zero If bit i of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get a proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction. Skip if [m].i=0 TC2 3/4 TABRDC [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
Move ROM code (current page) to TBLH and to the data memory The low byte of the ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte is transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
TABRDL [m] Description
Move ROM code (last page) to TBLH and to the data memory The low byte of the ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte is transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4
Operation Affected flag(s)
XOR A,[m] Description Operation Affected flag(s)
Logical XOR accumulator with data memory Data in the accumulator and indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m] TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
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March 15, 2000
HT827A0
XORM A,[m] Description Logical XOR data memory with accumulator Data in the indicated data memory and accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The zero flag is affected. [m] ACC XOR [m] TC2 3/4 XOR A,x Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
Logical XOR immediate data to the accumulator Data in the the accumulator and specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The zero flag is affected. ACC ACC XOR x TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4
Operation Affected flag(s)
48
March 15, 2000
HT827A0
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright O 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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March 15, 2000

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